Method and arrangement for minimizing skew

ABSTRACT

A method and an arrangement minimizes skew in digital synchronous systems. The arrangement includes N number of driver circuits, each of which has a P number of buffer units, of which each has an input and an output. Each driver circuit has a delay of δ 1 , δ 2 , δ 3 , δ 4  . . . δ N . Of these buffer units, N-1 buffer units are reserved while the inputs of the remaining buffer units P-(N-1) are connected mutually in parallel. The reserved buffer units are used as follows. A signal deriving from a signal source is applied to an input of a first buffer unit in each of the N-number of driver circuits, where the signal is subjected to a delay. The one-time delayed signal from a driver circuit is then delayed once, and only once, in the reserved buffer units of each of the remaining driver circuits. This procedure is repeated for each of the once-delayed signals on the outputs of the first buffer unit in each of the remaining N-1 driver circuits. Output signals which are mutually delayed by a time delay of δ 1  +δ 2  +δ 3  +δ 4  . . .+δ N  appear on the outputs of the buffer units in each of the driver circuits, the inputs of these buffer units being connected in parallel.

TECHNICAL FIELD

The present invention relates to a method and to an arrangement forminimizing skew in synchronous digital systems.

More specifically, the invention relates to a method and to anarrangement which will guarantee a smallest time difference betweensignals that are delivered to a first number of driver circuits each ofwhich includes a number of buffer units each having an input and anoutput, and each driver circuit having a respective time delay, saidsignals being generated in response to a signal, generated by a signalsource, which is applied to an input of a buffer unit on each of thedriver circuits, wherein the signal from said signal source is passedthrough the driver circuits in a manner such that the output signalshave, in relation to the signal from said signal source, a total delaywhich is the sum of the delay in each driver circuit.

BACKGROUND ART

In a synchronous digital system, a master or system clock is distributedto those circuits that perform synchronous functions. In order tomutually coordinate these synchronous functions, it is essential thateach functional element is connected to a clock line in which thevariation of the flank of a clock pulse, within narrow limits, willoccur simultaneously with the occurrence of a corresponding flank onremaining distributed clock pulses that occur in other functionalelements. The time difference between the flank of a clock pulse on aclock line and a corresponding flank of a corresponding clock pulse onanother clock line, where both of the clock pulses are derived from thesame master or system clock, is called skew and is measured innanoseconds.

Since a single master clock is unable to drive a large number of drivercircuits in a synchronous system, groups of local clock lines areproduced from the main clock pulse, by utilizing driver circuits whicheach consist of a plurality of buffer units. Skew is caused by thedifference in the response time of different driver circuits.

A method and an arrangement of the kind defined in the introduction aredescribed in European Patent Application No. 0,362,691. This knownarrangement includes two driver circuits from which a total of six clocksignals is obtained. These six clock signals have a delay which amountsto the total or combined delay of each of the two driver circuits. Whenadditional clock signals are required, it is necessary to use furtherdriver circuits. The European patent application, however, fails todisclose how this problem shall be solved.

A conceivable expansion of the principle described in the Europeanpatent application would be to duplicate the known arrangement, i.e., touse two arrangements of the kind illustrated, and connect each of thearrangements to the clock generator. This solution, however, would meanthat the clock signals from the two arrangements would mutually presenta delay which can vary within much wider limits than the delay occurringbetween the clock signals in each arrangement.

Another solution to the problem would be to manufacture driver circuitsin which the number of buffer units is much greater than the four bufferunits shown. Present-day technology enables a driver circuit to beproduced which has up to thirty-two buffer units, wherein the skew ofthe driver circuit is retained within one or a few nanoseconds.

These known solutions cannot be applied, at least with a reasonablenumber of clock circuits and a reasonable number of driver circuits,when hundreds of IC-circuits shall be driven synchronously. Severalparallel-connected driver circuits are required in order to drive thehigh capacitive load presented by so many IC-circuits. Circuitmanufacturers offer solutions with matched circuits or special clockdrivers and are able to guarantee a smallest skew between differentcircuits, although this solution is not sufficiently effective whenhundreds of IC-circuits are to be driven synchronously.

SUMMARY OF THE DISCLOSURE

The present invention is a development of the principle described in theaforesaid European Patent Application and is achieved by reserving anumber of buffer units on each of the driver circuits and utilizing thereserved buffer units to delay the signal repeatedly. More specifically,the signal that has been delayed once on the output of the buffer unitin a driver circuit is passed through each of the remaining drivercircuits. This procedure is repeated for each of the once-delayedsignals in the remaining driver circuits. All output signals from thedriver circuits will mutually present a skew which is equal to the sumof the delay in each driver circuit.

BRIEF DESCRIPTION OF THE DRAWING

The invention will now be described with reference to the accompanyingdrawing, in which

FIG. 1 illustrates a known skew minimizing circuit;

FIG. 2 illustrates a first inventive circuit; and

FIG. 3 illustrates a second inventive circuit.

DETAILED DESCRIPTION OF THE DISCLOSURE

The known circuit illustrated in FIG. 1 includes two driver circuits N₁,N₂, each of which has a total of nine buffer units (not shown). Eachbuffer unit has an input and an output. These inputs and outputs areshown schematically in the Figures, by means of lines. The delay in thedriver circuit N₁ is designated δ₁ and the delay in the driver circuitN₂ is designated δ₂. The manufacturer guarantees that the delay in eachdriver circuit will amount to a specified time at maximum. A typicalmaximum delay time for a driver circuit of type 74ABT827 having tenbuffer units is 4.8 nanoseconds. A clock pulse (not shown) arrives on aline 1 and is distributed via a line 2 to the input of each buffer unitin each of the two driver circuits N₁ and N₂. The clock signal appearson the output of the buffer unit used in the driver circuit N₁ at a timedelay δ₁ relative to the time t₀, where t₀ is the time at which theclock pulse arrived on the input. The delayed clock pulse is led to theparallel-coupled inputs of the buffer units of the driver circuit N₂ viaa line 3. The clock signal will thus appear on corresponding outputsdelayed by the time delay δ₁ +δ₂. The clock pulse on line 1 also passesto the input of a buffer unit in the driver circuit N₂, via the line 2.The clock pulse appears on the output of this buffer unit delayed bytime δ₂, and is led to the parallel-coupled inputs of the remainingeight buffer units in the driver circuit N₁, via line 4. The clock pulsesignals delayed on the eight lines are now subjected to a last delay inthe driver circuit N₁ prior to appearing on the outputs of the bufferunits of the driver circuit N₁, where the clock signals have the totaldelay δ₁ +δ₂, i.e., the same delay as the output signals from the drivercircuit N₂. This method guarantees a skew, or a mutual time delay, of δ₁+δ₂ between all of the clock signals leaving the two driver circuits N₁and N₂.

FIG. 2 illustrates an inventive arrangement, in which three drivercircuits N₁, N₂ and N₃ are used. In relation to the circuit illustratedin FIG. 1, there is obtained a larger number of synchronized clocksignals which mutually have a time delay that amounts to the sum of eachdriver circuit delay, in this case δ₁ +δ₂ +δ₃, where δ₁ is the delay inthe driver circuit N₁, δ₂ is the delay in the driver circuit N₂ and δ₃is the delay in the driver circuit N₃. Each driver circuit N₁ -N₃includes P buffer units (not shown), each having an input and an output.Of these buffer units, M number of buffer units are reserved forprocessing the clock signal on the line 1 in a manner described in moredetail herebelow. More specifically, N-1 number of buffer units arereserved, where N is an integer which denotes the number of drivercircuits. Thus, M=N-1. In the FIG. 2 embodiment, N=3 and thus M=2. Theinputs of the remaining P-M reserved buffer units in each of the drivercircuits N₁ -N₃ are mutually connected in parallel in the mannerillustrated. The inputs of the M reserved buffer units are referencedM₁, M₂ in each of the driver circuits. The driver circuits and thereserved buffer units are numbered in sequence in the following, so asto facilitate presentation. A numbered sequence, however, is notessential to the invention.

The clock signal on the line 1 is now distributed to each driver circuitN₁ -N₃ via lines 5, 6 and 7, so that the signal will lie on the input ofthe buffer units M₁ in each of the driver circuits.

The clock signal delayed by δ₁ on the output of the buffer unit M1 inthe first driver circuit N₁ is passed on a line 8 to the input of thesecond buffer unit M₂ in the second driver circuit N₂, where it isdelayed by δ₂ before appearing on the output of the buffer unit M₂. Aline 9 connects the output of the buffer unit M₂ to theparallel-connected inputs of the P-M parallel-connected inputs on thethird driver circuit N₃. The clock signal delayed by the time delay δ₁+δ₂ is subjected to a last delay δ₃ in the remaining unreserved P-Mbuffer units in the driver circuit N₃ before appearing on each of theoutputs of the remaining P-M buffer units. The arrow heads adjacent thedriver circuit N₃ represent these output signals, which are mutuallydelayed by time delay δ₁ +δ₂ +δ₃.

A similar procedure takes place for the clock signal on the line 6. Morespecifically, a line 10 connects the output of the first buffer unit inthe second driver circuit N₂ with the input of the second buffer unit inthe third driver circuit N₃. A clock signal delayed by time delay δ₂ +δ₃now lies on the output of the second buffer unit in the driver circuitN₃. A line 11 connects the output of the second buffer unit in the thirddriver circuit N₃ to the P-M parallel-connected inputs of the bufferunits in the first driver circuit N₁, in which the δ₂ +δ₃ delayed clocksignal is subjected to a last delay δ₁, so that P-M output signalsmutually delayed by the time delay δ₂ +δ₃ +δ₁ exist on the remaining P-Mbuffer units, these P-M output signals being represented by the arrowheads at N₁.

The same procedure is repeated for the clock signal on the line 7, whichpasses to the input of the first buffer unit M₁ in the third drivercircuit N₃. A line 12 connects the output from this first buffer unit tothe input of the second buffer unit M₂ in the first driver circuit N₁.Thus, the clock signal on the output of this second buffer unit has beendelayed by δ₃ +δ₁. A line 13 connects the output of the second bufferunit M₂ in the first driver circuit N₁ to the P-M parallel-connectedinputs of the remaining buffer units in the second driver circuit N₂.The twice delayed signals are subjected in this second driver circuit toa last delay, so that P-M output signals mutually delayed by δ₃ +δ₁ +δ₂will lie on remaining P-M outputs of the second driver circuit N₂.

It will be evident from the aforegoing that clock signals whose mutualdelay, or skew, now amounts to δ₁ +δ₂ +δ₃ lie on the P-M outputs of eachof the driver circuits N₁, N₂ and N₃.

In the FIG. 2 illustration, the driver circuits N₁, N₂ and N₃ arearranged in a linear row, one after the other. In an alternativeembodiment, however, the driver circuits N₁, N₂ and N₃ may be disposedin a rotational-symmetrical relationship, so that the lines 5, 6, 7 willhave mutually equal lengths and so that the lines 8, 9, 10, 11 and 12will also be essentially of equal lengths. A rotational-symmetricalarrangement of this nature is shown, for instance, in FIG. 3, where thedriver circuits are four in number.

In the case of the FIG. 3 embodiment, the number of driver circuits N=4,and thus the number of reserved buffer units are N-1=M=3. The M reservedbuffer units are numbered in the order sequence M₁, M₂ and M₃ in each ofthe drive units N₁, N₂, N₃ and N₄. The clock signal on the line 1 isdistributed to the input of the first buffer unit on each of the fourdriver circuits, by means of lines 14, 15, 16 and 17. The driver circuitN₁ has a delay of δ₁, the driver circuit N₂ has a delay of δ₂, thedriver circuit N₃ has a delay of δ₃ and the driver circuit N₄ has adelay of δ₄. The output of the first buffer unit M₁ in the first drivercircuit N₁ is connected by a line 18 to the input of the second bufferunit in the second driver circuit N₂. The output of the second bufferunit in the second driver circuit N₂ is connected by a line 19 to theinput of the third buffer unit in the driver circuit N₃. The clocksignal on the output of the third buffer unit will thus be delayed by atime delay of δ₁ +δ₂ +δ₃. The output of the third buffer unit in thethird driver circuit is connected to the parallel-connected inputs ofthe inputs of the remaining P-M buffer units, where the three timesdelayed clock signal is subjected to a last delay δ₄ prior to appearingon the outputs of said P-M buffer units, at which the clock signals aremutually delayed by the time delay δ₁ +δ₂ +δ₃ +δ₄.

The output of the first buffer unit in the second driver circuit N₂ isconnected to the input of the second buffer unit in the third driverunit N₃. The output of the second buffer unit in the third drivercircuit N₃ is connected to the input of the third buffer unit in thefourth driver circuit N₄, and the output from the last-mentioned bufferunit is connected to the parallel-connected, remaining buffer units inthe first driver circuit N₁. Clock signals which are mutually delayed bythe time delay δ₂ +δ₃ +δ₄ +δ₁ thus lie on the P-M outputs of the firstdriver circuit N₁.

The connecting procedure described above is also applied in respect ofthe clock signal on the line 16, wherein the first buffer unit M₁ in thedriver circuit N₃ is connected to the input of the second buffer unit inthe fourth driver circuit N₄, and so on, until the clock signal delayedby the time delay δ₃ +δ₄ +δ₁ lies on the parallel-connected inputs ofthe second driver circuit N₂. Clock signals which are mutually delayedby the time delay δ₃ +δ₄ +δ₁ +δ₂, i.e., delayed to the same extent asthe output signals in the driver circuits N₄ and N₁, thus lie onremaining P-M outputs of the driver circuit N₂.

The connecting procedure described above is also applied in respect ofthe clock signal on the line 17. Thus, the clock signal delayed by thetime delay δ₄ +δ₁ +δ₂ is distributed to the parallel-connected inputs ofthe third driver circuit N₃ prior to being subjected to a last timedelay δ₃ in the driver circuit N₃. Thus, clock signals having a mutualdelay equal to δ₁ +δ₂ +δ₃ +δ₄ will now also lie on the P-M outputs ofthe third driver circuit N₃.

It will be evident from the aforegoing that the N·(P-M) output signalson the four driver circuits will all be delayed mutually by a time delayof δ₁ +δ₂ +δ₃ +δ₄.

It will be obvious that the described principle can be applied toconnect together any desired number N of driver circuits. By reservingN-1 buffer units in each driver circuit, the clock signal can beprepared for successive delays in each of N-2 driver circuits beforebeing subjected to a final delay. At the Nth delay, i.e., at the last orfinal delay, the N-1 delayed clock signal is subjected to a delay whichrenders the total delay of the clock signal equal to the delay of eachof the N-number of driver circuits. A similar procedure is carried outfor each of the clock signals on the first buffer unit in each of theremaining N-1 driver circuits.

It is assumed in the examples illustrated in FIGS. 2 and 3 that thebuffer units are numbered in an ordered sequence, such that the outputof, e.g., the second buffer unit in the driver circuit is connected tothe output of the third buffer unit in a next following driver circuit.It will be understood, however, that this need not necessarily be thecase, since it will suffice to connect the output from said secondbuffer unit to the input of any buffer unit whatsoever in thenext-following driver circuit. The essential feature is, of course, thatthe clock signal from the preceding driver circuit is subjected to delayin one of the buffer units in the following driver circuit. In otherwords, the order sequence between the buffer units of a driver circuit,any driver circuit whatsoever, may be reversed.

In the case of the FIG. 2 and FIG. 3 examples, the driver circuits havebeen numbered in an ordered sequence such that a clock signal will passfrom, e.g., the driver circuit N₂ to the driver circuit N₃. It will beunderstood, however, that a clock signal may alternatively pass from thedriver circuit N₂ to the driver circuit N₄, for instance, and to passback from the driver circuit N₄ to the driver circuit N₃ and from thedriver circuit N₃ to the driver circuit N₁.

It is important to the present invention that in an arrangementconsisting of N number of driver circuits, the clock signal from theclock-signal source shall be distributed to each of the driver circuitsand each of the clock signals shall thereafter be passed through each ofthe remaining driver circuits in a manner such that the signals will besubjected to at most one delay in each driver circuit.

As will be evident from the above description, P is an integer of anydesired value. On the other hand, M is the number of driver circuitsused, and the number of reserved buffer units will be given by thenumber of driver circuits used.

When N driver circuits each having P buffer units are connectedtogether, the number of clock signals will thus equal N°(P-N+1). Themaximum number of clock signals from one construction is obtained whenthe number of driver circuits N is (P+1)/2.

It will be understood that the aforedescribed and illustratedembodiments of the invention can be modified and changed in many wayswithin the scope of the following claims.

I claim:
 1. A method of generating a large number of clock pulses havinga time difference therebetween which at maximum equals a predefinedvalue, said method comprising the steps of:feeding a master clock pulsefrom a clock pulse source in parallel to a first number of drivercircuits, each driver circuit having a respective skew and eachcomprising a first plurality of buffer circuits, each buffer circuithaving an input and an output, by feeding said master clock pulse to afree input, thus subjecting said master clock pulse to a first delay,feeding each one of said once delayed signals to a free input of afollowing driver circuit in order to subject said once delayed signalsto a second delay, wherein said step of feeding the delay signal isrepeated until a total number of delays equals said first number ofdriver circuits minus 1, thus generating at each of the driver circuitsan intermediate delayed signal which has been delayed said total numberof times, eventually feeding said intermediate delayed signals inparallel to a second number of free buffer circuits of a respectivefollowing driver circuit so as to subject said intermediate delayedsignals to a final delay, thus generating at the outputs of saidnon-used buffer circuits a corresponding second number of clock pulses,said second number of clock pulses appearing at each one of said drivercircuits together forming said large number of clock pulses having atime difference therebetween which at maximum is the sum of the skews ofeach one of the driver circuits and which forms said predefined value.2. An arrangement for generating a large number of clock pulses having atime difference therebetween which at maximum equals a predefined value,comprising:a first number of driver circuits having a respective skewand each comprising a first plurality of buffer circuits, each buffercircuit having an input and an output, a clock pulse source forgenerating a master clock pulse which is fed in parallel to a firstbuffer circuit at each one of said driver circuits so as to be subjectedthereby to a first delay, at each driver circuit said output of saidfirst buffer circuit being connected to a free second buffer circuit inanother driver circuit in which the once delayed signals are subjectedto a second delay, wherein at each driver circuit said output of saidsecond buffer circuit being connected to a free third buffer circuit inanother driver circuit in which said twice delayed signals are subjectedto a third delay, repeatingly connecting the output of a buffer circuitto a following free buffer circuit as many times as said first number ofdriver circuits minus 1 to produce intermediate delayed signals, whereineach of the intermediate delayed signals, at each driver circuit,eventually is connected in parallel to a second number of free buffercircuits of a following driver circuit, wherein the output signals fromsaid second number of buffer circuits together will form said largenumber of clock pulses which have a time difference therebetween whichat maximum is the sum of the skews inherent in each of the drivercircuits, said sum forming said predefined value.
 3. An arrangement forgenerating a large number of clock pulses in accordance with claim 2,wherein said driver circuits are disposed rotationally-symmetrical on acircuit board, and conductors between said buffer circuits, which areused to produce said repetitive delays of the master clock pulse, aresymmetrical.